Marco Caetano Lazarine Bontorin :: MSc. Student in Computer Architecture and Sensor Networks

Marco Caetano Lazarine Bontorin CV Lattes
Federal University of Paraná
Email: marco at inf dot ufpr dot br

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Research domains

Embedded systems

Wireless sensor networks

Sensor node architecture

Power saving in sensor nodes

Field Programmable Gate Arrays (FPGA)

Finished projects

Techniques of placement and retiming for FPGA energy consumption reduction
Bachelor of Computer Science Conclusion Work finished in 2008, Title: "A study about efficient storage of routing tables in Network Processors". In this work was made a research about network processors and different techcnics used to implement routing tables. Also it was written a simulator of a network processor using a TCAM to store and look up for the next hop in the routing table. full PDF