Description
Each day, more and more functionalities have been added to mobile devices. In order to comply with
these new functionalities, the system must have high processing speed and energy efficient hardware. The reasons for these
needs are that there are applications which require real time processing and that the mobile devices are often powered by scarce
energy sources.
Mobile devices are usually powered by batteries. These batteries have a limited charge which sometimes need to be saved. As an extreme example we have the sensor networks. These networks can have mobile or static nodes, but in both cases they are often powered by batteries and communicate by radio frequency waves. If they are thrown in a forest or in the sea, sometimes it's impossible to have physical access to them, then its energy source must be wisely used in order to keep the network working for most of the possible time. An more ordinary example are the cell phones. The cell phones is one of the greatest recent example of functionality increase. Every one agrees that it's not feaseble using an such device that must be charged more than twice a day, so it must have some mechanism to efficiently use the energy available.
These devices are usually made up of microprocessors, microcontrolers or ASICs as its main processing unit. ASICs are for sure the most efficient choice in all aspects, but it's the least flexible. Once one circuit is manufactered, it's impossible changing its functionality and if it's needed, a new circuit must be produced. On the other hand, general purpose processors such that present in today's desktop computers, are the most flexible, capable of implementing any given new funcionality you want to add to your device, but it has limited speed because of its inherent sequencial execution.
An alternative which appears to have a good trade off between efficiency and flexibility are the FPGAs. These are reconfigurable devices which can implement any functionality. To make it possible, there are programming technologies (usually SRAM cells) available which are used to control internal switches. FPGAs can have a good trade off between the hardware paralelism and software flexibility need to implement the near future mobile devices applications. So, why it's not largely used in today's mobile devices?
FPGAs are known to be power hungry. It's inherent flexibility is reached mainly through the use of general purpose logic blocks and general purpose routing resource, the last one been the major problem for energy saving. There has been many efforts to saving energy in FPGAs. FPGA vendors such Actel, have been producing devices with new tecnologies which are more energy friendlies. FPGA CAD vendors are making power-aware flows, that take into account energy estimates of the circuit to generate the final circuit that will be programmed into the FPGA.
One of the techniques used to save energy is pipelining. Pipelining consists of inserting registers in certain points of the circuit. It has been used for a long time in microprocessors for clock frequency increasing and can be used for the same thing in FPGAs. However, for reducing energy consumption in FPGAs, pipelining is commonly used to reduce glitching. Glitching is one of the main causes of dynamic energy dissipation, which in turn is the main contributor to the total FPGA energy dissipation.
Pipelining can be implemented on System level, when the designer is writing the circuit in a hardware description language or after logical synthesis inserting the register in the netlist file. Recently, there has been works which are doing retiming of the pipeline registers during placement. FPGA placement is one of the key steps on the FPGA design flow that involves atribute a logic block in the netlist to a (x,y) position in a FPGA. This will have direct impact in routing, so will greatly influenciate the final energy and speed efficiency.
This project aims to propose simultaneously a new FPGA placement and retiming technique able to efficiently place a circuit and making the retiming in order to reduce the FPGA energy consumption. It will be carried out using ant-based agents which will perform a repositioning and retiming of the circuit based on local agent information leading to a more energy efficient final circuit.
Methodology
To achieve the project goals, we will make use of the Versalile Place and Route (VPR) tool, version 5.0, specifically the version which have an detailed power model that can give an estimation of the power consumption of the circuit (this software can be found here). The VPR CAD tool is the most used academic tool for FPGA placement and routing. The current version implements a Simulated-Annealing based placement which aims to do the most critical path delay and path length efficient placement. We will change the current placement technique and introduce the ideas described before.
Accomplishments
Marco Bontorin - Master student
Crystiane Meira - Undergraduate student
Aldri Santos - Advisor
Michele Nogueira - Advisor
Mobile devices are usually powered by batteries. These batteries have a limited charge which sometimes need to be saved. As an extreme example we have the sensor networks. These networks can have mobile or static nodes, but in both cases they are often powered by batteries and communicate by radio frequency waves. If they are thrown in a forest or in the sea, sometimes it's impossible to have physical access to them, then its energy source must be wisely used in order to keep the network working for most of the possible time. An more ordinary example are the cell phones. The cell phones is one of the greatest recent example of functionality increase. Every one agrees that it's not feaseble using an such device that must be charged more than twice a day, so it must have some mechanism to efficiently use the energy available.
These devices are usually made up of microprocessors, microcontrolers or ASICs as its main processing unit. ASICs are for sure the most efficient choice in all aspects, but it's the least flexible. Once one circuit is manufactered, it's impossible changing its functionality and if it's needed, a new circuit must be produced. On the other hand, general purpose processors such that present in today's desktop computers, are the most flexible, capable of implementing any given new funcionality you want to add to your device, but it has limited speed because of its inherent sequencial execution.
An alternative which appears to have a good trade off between efficiency and flexibility are the FPGAs. These are reconfigurable devices which can implement any functionality. To make it possible, there are programming technologies (usually SRAM cells) available which are used to control internal switches. FPGAs can have a good trade off between the hardware paralelism and software flexibility need to implement the near future mobile devices applications. So, why it's not largely used in today's mobile devices?
FPGAs are known to be power hungry. It's inherent flexibility is reached mainly through the use of general purpose logic blocks and general purpose routing resource, the last one been the major problem for energy saving. There has been many efforts to saving energy in FPGAs. FPGA vendors such Actel, have been producing devices with new tecnologies which are more energy friendlies. FPGA CAD vendors are making power-aware flows, that take into account energy estimates of the circuit to generate the final circuit that will be programmed into the FPGA.
One of the techniques used to save energy is pipelining. Pipelining consists of inserting registers in certain points of the circuit. It has been used for a long time in microprocessors for clock frequency increasing and can be used for the same thing in FPGAs. However, for reducing energy consumption in FPGAs, pipelining is commonly used to reduce glitching. Glitching is one of the main causes of dynamic energy dissipation, which in turn is the main contributor to the total FPGA energy dissipation.
Pipelining can be implemented on System level, when the designer is writing the circuit in a hardware description language or after logical synthesis inserting the register in the netlist file. Recently, there has been works which are doing retiming of the pipeline registers during placement. FPGA placement is one of the key steps on the FPGA design flow that involves atribute a logic block in the netlist to a (x,y) position in a FPGA. This will have direct impact in routing, so will greatly influenciate the final energy and speed efficiency.
This project aims to propose simultaneously a new FPGA placement and retiming technique able to efficiently place a circuit and making the retiming in order to reduce the FPGA energy consumption. It will be carried out using ant-based agents which will perform a repositioning and retiming of the circuit based on local agent information leading to a more energy efficient final circuit.
Methodology
To achieve the project goals, we will make use of the Versalile Place and Route (VPR) tool, version 5.0, specifically the version which have an detailed power model that can give an estimation of the power consumption of the circuit (this software can be found here). The VPR CAD tool is the most used academic tool for FPGA placement and routing. The current version implements a Simulated-Annealing based placement which aims to do the most critical path delay and path length efficient placement. We will change the current placement technique and introduce the ideas described before.
Accomplishments
- Study about pipelining and retiming
- Undestanding the current VPR power-aware placement implementation
- Reproduce some known experiments with the VPR in order to validate the current code for future use
- Propose a local optimization solution for FPGA placement using ant-based agents
- Implementing the ant-based FPGA placement on the power-aware VPR 5.0
- Validate the implementation with the assistance of the available regression tests, and previous version results
- Propose and implement retiming technique considering the proposed ant-based FPGA palcement
- Evaluate the solution by comparing the VPR results with the results of previous similar works
- 03/2009 - 03/2011
Marco Bontorin - Master student
Crystiane Meira - Undergraduate student
Aldri Santos - Advisor
Michele Nogueira - Advisor
- Universidade Federal do Paraná
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- Núcleo de Redes Sem-fio e Redes Avançadas
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- Bio-inspired Wireless Networking Team (BioNet)
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