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-- Company:
-- Engineer:
-- 
-- Create Date:    13:09:09 03/26/2010
-- Design Name:
-- Module Name:    FullAdder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FullAdder is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           C : in  STD_LOGIC;
           SUM : out  STD_LOGIC;
           COUT : out  STD_LOGIC);
end FullAdder;

architecture Behavioral of FullAdder is

begin
    SUM <=     (not a and not b and c) or
                (a and not b and not c) or
                (a and b and c) or
                (not a and b and not c);
    COUT <=     (a and c) or (b and c) or (a and b);
    


end Behavioral;